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[Other resource] fir

Description: Verilog 程序， 实现4阶 fir-filter滤波器。
Platform: | Size: 1740 | Author: 左麟 | Hits:

[VHDL-FPGA-Verilog] firISPdesign

Description: fir ISP design fir VHDL VHDL编程滤波的硬件描述语言实现，包括VHDL语言和verilog语言-fir fir VHDL design ISP programming VHDL hardware description of the filter language , including the VHDL language and verilog
Platform: | Size: 112640 | Author: xiong | Hits:

[VHDL-FPGA-Verilog] fir_finall

Description:
Platform: | Size: 1024 | Author: 刘东 | Hits:

[VHDL-FPGA-Verilog] Pall_FIR

Description: FIR低通滤波器得设计，采用并行算法设计-FIR low-pass filter was designed in parallel algorithm design
Platform: | Size: 2004992 | Author: luyingc | Hits:

[MacOS develop] firVerilog

Description: 里面是一个FIR滤波器的VHDL语言 具体的功能里面有详细的介绍 对毕业设计者很有帮助的 -There is a FIR filter VHDL language specific features which are detailed introduction to the graduate designers helpful
Platform: | Size: 4096 | Author: 丛宇 | Hits:

[VHDL-FPGA-Verilog] firOK

Description: 17阶FIR滤波器VHDL代码及说明文档 下载立即可以仿真-17FIR 瞬 VHDL 爰?说 牡 苑
Platform: | Size: 1029120 | Author: fangyingjie | Hits:

[VHDL-FPGA-Verilog] fir6dlms

Description: lms的verilog代码，我找了好久在才找的的，好东西，大家一起学习-LMS of the Verilog code, I am looking for a long time before looking at the good things we can work together to learn
Platform: | Size: 1024 | Author: 李允 | Hits:

[VHDL-FPGA-Verilog] fir_using_FPGA

Description: 基于verilog的fir滤波，并带matlab仿真-Verilog-based filtering of fir and bring matlab simulation
Platform: | Size: 24576 | Author: 宇天 | Hits:

[VHDL-FPGA-Verilog] fir_parall

Description: 基于verilog的fir滤波器设计，用的并行结构。在前面基础上加入四级流水（加法器，并行乘法器，乘法结果相加两级），通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), through the verification.
Platform: | Size: 3072 | Author: 张堃 | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 基于FPGA的自适应滤波器的实现。采用Verilog编程，2阶滤波器。-FPGA-based realization of the adaptive filter. Using Verilog programming, 2-order filter.
Platform: | Size: 12288 | Author: 田文军 | Hits:

[Linux-Unix] Linux_bc

Description: 对vga接口做了详细的介绍，并且有一 ·三段式Verilog的IDE程序，但只有DMA ·电子密码锁，基于fpga实现，密码正 ·IIR、FIR、FFT各模块程序设计例程， ·基于逻辑工具的以太网开发，基于逻 ·自己写的一个测温元件（ds18b20）的 ·光纤通信中的SDH数据帧解析及提取的 ·VHDL Programming by Example（McGr ·这是CAN总线控制器的IP核，源码是由 ·FPGA设计的SDRAM控制器，有仿真代码 ·xilinx fpga 下的IDE控制器原代码, ·用verilog写的，基于查表法实现的LO ·精通verilog HDL语言编- up:in STD_LOGIC down:in STD_LOGIC run_stop:in STD_LOGIC wai_t: in std_logic_vector(2 downto 0) lift:in std_logic_vector(2 downto 0) ladd: out std_logic_vector(1 downto 0) ) end control
Platform: | Size: 18683904 | Author: liuzhou | Hits:

[Communication-Mobile] fir

Description: 用verilog实现fir滤波器,实现了一个8阶的fir滤波器-design the fir filter use verilog lanuage
Platform: | Size: 1024 | Author: 叶敏 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 利用Verilog语言编写的FPGA作为数字fir滤波器的程序，在编译器中调试通过，可以作为模块调用。-the model of fir digital cr which is written of verilog language.
Platform: | Size: 1024 | Author: saul | Hits:

[VHDL-FPGA-Verilog] fir_lms

Description: 一个不错的关于lms算法的verilog代码，算然只有两级，但是对了解lms用HDL描述有很好的理解作用。希望对大家有用~-A good lms algorithm on the verilog code, development environment, I can not find, even if the vhdl it! We hope to be useful
Platform: | Size: 1024 | Author: onion | Hits:

[VHDL-FPGA-Verilog] fir

Description: 基于verilog的 FIR低通滤波器的实现(Implementation of FIR low pass filter based on Verilog)
Platform: | Size: 140288 | Author: yaaaan | Hits:

[VHDL-FPGA-Verilog] 数字信号处理的FPGA实现-第三版-verilog源程序

Description: 数字信号处理的FPGA实现, 包括了FPGA基础知识，浮点运算，信号处理的FIR FFT等，附录包含源代码(Digital signal processing FPGA implementation, including the basic knowledge of FPGA, floating point operations, signal processing FIR, FFT, etc., the appendix contains the source code)
Platform: | Size: 4568064 | Author: btty | Hits:

[Other] 基于FPGA和IP核的FIR低通滤波器

Description: 用verilog语言实现数字电路低通滤波器(Implementation of digital circuit low-pass filter using Verilog language)
Platform: | Size: 39936 | Author: 曾今的1994 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: FIR filter in verilog for xilinx ise design suit
Platform: | Size: 190464 | Author: addy007 | Hits:

[VHDL-FPGA-Verilog] Verilog的135个经典设计实例

Description: Verilog的135个经典设计实例，部分摘录如下：【例 9.23】可变模加法/减法计数器【例 11.7】自动售饮料机【例 11.6】“梁祝”乐曲演奏电路【例 11.5】交通灯控制器【例 11.2】4 位数字频率计控制模块【例 11.1】数字跑表【例 9.26】256×16 RAM 块【例 9.27】4 位串并转换器【例 11.8】多功能数字钟【例 11.9】电话计费器程序【例 12.13】CRC 编码【例 12.12】（7，4）循环码纠错译码器【例 12.10】（7，4）线性分组码译码器【例 12.7】11 阶FIR 数字滤波器。。。。。。。(135 classic examples of Verilog design)
Platform: | Size: 167936 | Author: 三棵树机务段 | Hits:

[hardware design] fir滤波器

Description: FIR滤波器，verilog编写，可以正常使用(FIR filter, written by verilog, can be used normally, very good)
Platform: | Size: 1031168 | Author: happytian | Hits:
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